if(typeof(JsCommentJson) == 'undefined') JsCommentJson = {}; JsCommentJson.usercommentedlist=[{"id":"3720757","pid":"235708","username":"pxlei_nuc","pubdate":"2008-08-25 15:33:52","title":"CPLD\u3001FPGA\u5f00\u53d1\u4e0e\u5e94\u7528","commentnums":"7","self":"\/source\/468982","visiteip":"60.191.78.*","description":"\u8fd8\u53ef\u4ee5\u7684\u4e1c\u897f","supportnums":"0","opposenums":"0"},{"id":"3606214","pid":"208140","username":"pxlei_nuc","pubdate":"2008-08-07 19:42:02","title":"\u4e32\u53e3de\u901a\u8baf","commentnums":"2","self":"\/source\/461627","visiteip":"124.42.13.*","description":"\u8c22\u8c22\u697c\u4e3b\uff0c\u5b66\u4e60\u5b66\u4e60","supportnums":"0","opposenums":"0"},{"id":"3492601","pid":"235708","username":"pxlei_nuc","pubdate":"2008-08-01 11:15:16","title":"CPLD\u3001FPGA\u5f00\u53d1\u4e0e\u5e94\u7528","commentnums":"7","self":"\/source\/468982","visiteip":"218.5.3.*","description":"\u96be\u7684\u7684\u597d\u4e1c\u897f","supportnums":"0","opposenums":"0"},{"id":"3198170","pid":"235708","username":"pxlei_nuc","pubdate":"2008-07-15 17:11:43","title":"CPLD\u3001FPGA\u5f00\u53d1\u4e0e\u5e94\u7528","commentnums":"7","self":"\/source\/468982","visiteip":"159.226.167.*","description":"\u901f\u5ea6\u6709\u70b9\u6162\uff0c\u4e0d\u8fc7\u8fd8\u662f\u611f\u8c22\u5206\u4eab\u3002","supportnums":"0","opposenums":"0"},{"id":"3015490","pid":"235708","username":"pxlei_nuc","pubdate":"2008-07-03 18:52:58","title":"CPLD\u3001FPGA\u5f00\u53d1\u4e0e\u5e94\u7528","commentnums":"7","self":"\/source\/468982","visiteip":"121.229.183.*","description":"\u897f\u897f\u5076\u6570\u5927\uff1b","supportnums":"0","opposenums":"0"},{"id":"3015461","pid":"235708","username":"pxlei_nuc","pubdate":"2008-07-03 18:51:05","title":"CPLD\u3001FPGA\u5f00\u53d1\u4e0e\u5e94\u7528","commentnums":"7","self":"\/source\/468982","visiteip":"121.229.183.*","description":"\u8c22\u8c22\u7684\u8d44\u6599","supportnums":"0","opposenums":"0"},{"id":"2887708","pid":"235708","username":"pxlei_nuc","pubdate":"2008-06-25 16:28:15","title":"CPLD\u3001FPGA\u5f00\u53d1\u4e0e\u5e94\u7528","commentnums":"7","self":"\/source\/468982","visiteip":"218.104.49.*","description":"\u8c22\u8c22\u63d0\u4f9b\u8d44\u6599","supportnums":"0","opposenums":"0"},{"id":"2737910","pid":"235708","username":"pxlei_nuc","pubdate":"2008-06-15 23:17:14","title":"CPLD\u3001FPGA\u5f00\u53d1\u4e0e\u5e94\u7528","commentnums":"7","self":"\/source\/468982","visiteip":"125.83.28.*","description":"xiexie!!","supportnums":"0","opposenums":"0"},{"id":"2436023","pid":"208140","username":"pxlei_nuc","pubdate":"2008-05-20 22:53:12","title":"\u4e32\u53e3de\u901a\u8baf","commentnums":"2","self":"\/source\/461627","visiteip":"221.201.151.*","description":"\u770b\u770b\u518d\u8bc4\u8bba\r\n\u4e0d\u8fc7\u4e1c\u897f\u8fd8\u662f\u4e0d\u9519\u7684\uff0c\u8c22\u8c22\u5206\u4eab","supportnums":"0","opposenums":"0"}];